Summary
AMD has announced three Versal tamper-resistant devices that pair heterogeneous computing with a bonded sensor die designed to detect physical attacks on the silicon backside. Sampling is expected in the second half of 2027, with production planned for the first half of 2028.
AMD has announced three Versal tamper-resistant (TR) adaptive SoCs that combine heterogeneous computing with built-in protection against physical attacks on the silicon backside. The devices are designed for security-critical systems and add a sensor-based protection die bonded to the compute die using 3D active-on-active technology.
A bonded die monitors the silicon backside
AMD says the protection die covers the entire backside of the device, detects physical attacks and prevents the system from booting if the die is tampered with or removed. Integrating this protection with the compute device is intended to reduce reliance on separately designed security components and mechanical enclosures.
That integration could simplify system design for applications such as data-centre networking, fintech, defence and critical industrial infrastructure. AMD says customers commonly develop custom combinations of enclosures, ASICs and other components for this kind of protection; its integrated approach can save board area and simplify board design compared with those custom solutions.
The TR devices are based on AMD’s Versal AI Edge Series Gen 2 platform. The portfolio combines Arm CPUs, AI Engines, programmable logic, hard IP and connectivity. AMD lists up to 229,000 DMIPS of scalar compute, up to 369 INT8 TOPS and up to 543,000 LUTs. These figures describe the maximum capabilities across the portfolio, rather than a single configuration applying to every device.
Cryptographic features and availability
The devices also add hardware acceleration for post-quantum cryptography, including support for Module-Lattice-Based Digital Signature Algorithm (ML-DSA) and Stateless Hash-Based Digital Signature Algorithm (SLH-DSA). A hybrid boot flow can use multiple signature algorithms. Other additions include improvements to the application security unit key vault and a memory element aging sensor intended to add safeguards for cryptographic keys.
For detecting voltage glitches—brief disturbances that can interfere with device operation—AMD says the TR devices combine an improved Versal architecture glitch detector with a new orthogonal detector. The expanded coverage includes glitches occurring simultaneously across two voltage rails.
The three models are 2VE3358TR, 2VE3558TR and 2VE3858TR. AMD says each has a footprint-compatible standard counterpart available today, allowing customers to develop on the standard Versal platform and later transition to the corresponding TR device without rerunning synthesis or place and route.
The first Versal TR devices are expected to sample in the second half of 2027 and move to production in the first half of 2028. AMD describes the devices as tamper-resistant, not tamper-proof: protection applies to specified physical attack methods, with the applicable threat model and limitations set out in product documentation.