AMD has announced that select Versal RF Series adaptive SoCs will support native UCIe 1.1 connectivity, allowing them to communicate directly with specialised chiplets integrated in the same package. The company says the devices will support up to four independent UCIe-SP interfaces and up to two UCIe-AP interfaces, with multi-terabit-per-second aggregate in-package bandwidth.

AMD expects production chiplets to become available with select Versal RF Series devices in the fourth quarter of 2027. The announcement does not identify the exact device models, chiplet vendors or production workloads.

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What AMD is adding to Versal RF

UCIe, or Universal Chiplet Interconnect Express, is an open industry specification intended to standardise communication between chiplets, including chiplets potentially supplied by different vendors. A chiplet is a separately designed silicon die that is combined with other dies in a single semiconductor package.

AMD says the Versal RF Series will be the first Versal adaptive SoCs from the company to enable UCIe 1.1 connectivity. Initially, the selected devices are specified to include:

  • up to four independent UCIe-SP (standard-package) interfaces; and
  • up to two UCIe-AP (advanced-package) interfaces.

AMD describes the combined interface capability as providing multi-terabit-per-second aggregate bandwidth within the package. The announcement does not provide an independent benchmark for that figure or identify the exact Versal RF models that will support the interfaces.

Versal RF devices already combine several types of processing and signal-conversion hardware. AMD lists high-resolution RF data converters, dedicated digital-signal-processing intellectual property, AI Engines and programmable logic as components of the adaptive SoC architecture. The UCIe addition is intended to provide a direct in-package connection between the Versal RF device and additional specialised chiplets.

Possible chiplet functions identified by AMD include:

  • RF analogue front ends or data converters;
  • AI acceleration;
  • CPUs;
  • specialised GPU compute;
  • security engines;
  • communications processors; and
  • application-specific ASICs.

In this context, the proposed chiplet approach could allow different processing or signal-chain functions to be combined with the Versal RF device in one package.

How the chiplet connection works

An in-package interconnect links silicon dies inside the same semiconductor package. Because the link is inside the package rather than running across a circuit board, it can provide a shorter physical connection between components.

The intended architecture separates functions across specialised pieces of silicon. A Versal RF device could provide its combination of RF conversion, programmable logic, DSP and AI Engine resources, while a co-packaged chiplet could add another processor, accelerator, security function or communications block. UCIe supplies the standardised connection through which those components communicate.

This modular approach is different from putting every function into one large monolithic system-on-chip. AMD says chiplet-based integration can provide design flexibility and silicon-IP reuse, and may reduce development cost and shorten time to market compared with redesigning a large monolithic SoC. Those are intended benefits described by AMD; the announcement does not report measured development savings or a production customer result.

AMD also says the UCIe-enabled Versal RF devices can offer lower latency and improved power efficiency compared with its adaptive SoCs using board-level GTM2 serialised interfaces. The lower-latency and power claims are based on AMD internal analysis, not independent industry testing.

The power comparison uses estimated energy per bit for selected Versal RF Series devices with UCIe 1.1 and compares it with estimated energy per bit for AMD adaptive SoCs using board-level GTM2 interfaces. AMD's analysis includes the relevant interface circuitry, but the announcement does not provide an independent, apples-to-apples system benchmark.

What the performance claims establish

The announcement establishes the planned interface configuration and AMD's intended use of UCIe to connect Versal RF devices with co-packaged chiplets. It also establishes the advertised maximum of up to 80 TOPS of heterogeneous DSP compute for Versal RF Series devices.

TOPS means trillion operations per second. It is a throughput measure, not a direct measure of application performance, accuracy or power efficiency. The 80-TOPS figure therefore does not by itself show how a particular AI, communications or signal-processing workload will perform.

Similarly, multi-terabit-per-second aggregate bandwidth describes the combined advertised interface capacity. It does not establish the speed of a complete customer system, which would also depend on the connected chiplets, software, memory movement and workload.

The UCIe announcement does not provide:

  • independent measurements of bandwidth, latency or energy efficiency;
  • a production workload evaluation;
  • exact chiplet models or vendors;
  • confirmation that every third-party chiplet will interoperate in every configuration; or
  • evidence of a completed customer deployment.

AMD notes that some technologies may require third-party enablement or activation. As a result, support for the interface does not by itself guarantee that any arbitrary UCIe chiplet can be connected and used without additional technical work.

Timing and remaining uncertainties

AMD expects production chiplets to be available with select Versal RF Series devices in the fourth quarter of 2027. This is an expected production timeframe, not a confirmed commercial availability date.

The company says additional adaptive SoCs with UCIe support will be added as the market matures. Initially, however, the capability applies only to select Versal RF Series adaptive SoCs and not to the entire Versal product family.

AMD has not specified pricing, customer availability, sampling dates or India-specific availability in the supplied announcement. The exact models receiving UCIe support, the chiplet ecosystem available at production and the workloads that will benefit most remain unresolved.

Sources