Lenovo says Ducati Corse has expanded its high-performance computing (HPC) infrastructure to support development of the 2027 Desmosedici GP motorcycle, reporting a 50% reduction in 3D engine computational fluid dynamics (CFD) simulation time and a 30% reduction in structural-analysis time.

The system has more than 108 teraflops (TFLOPS) of combined theoretical double-precision computing performance. Lenovo also says that, compared with the previous generation of compute nodes, the expanded infrastructure provides roughly twice the available memory and about 48% more processing power.

The figures come from a Lenovo manufacturer account, not an independent benchmark report. The source does not identify the server models, processors, accelerators, software, networking architecture or workload methodology used to calculate the reported reductions.

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What changed

Ducati Corse is using the expanded Lenovo system during development of its 2027 motorcycle while continuing work on the 2026 bike, according to Lenovo. The simultaneous programmes are presented as a major engineering challenge because the team is still pursuing its current championship effort while preparing for a substantially changed technical package.

Lenovo describes the 2027 motorcycle as redesigned from the ground up in response to new MotoGP regulations. Its account identifies those changes as including:

  • 850cc engines;
  • reduced aerodynamics;
  • a ban on ride-height devices;
  • 100% sustainable fuel; and
  • a new tyre supplier.

The HPC infrastructure is being used to analyse components including intake and thermal systems, connecting rods and the crankshaft. Lenovo also links it to aerodynamic simulation and predictive engineering, with the aim of assessing designs before building physical parts.

Compared with the previous generation of compute nodes, the expansion provides roughly twice the available memory and about 48% more processing power. The practical effect of those changes depends on the workload and how the system is implemented.

How the HPC system fits Ducati’s workflow

CFD uses numerical calculations to model how fluids move and interact with surfaces. In motorcycle engineering, that can help analyse airflow and aerodynamic forces around the bike and its components. The source specifically refers to 3D engine CFD, as well as broader aerodynamic simulation.

Structural analysis uses computational models to estimate stresses, strains and deformation when a component is subjected to specified loads. This can help engineers evaluate parts such as connecting rods and crankshafts before physical testing or manufacture.

Lenovo says Ducati uses virtual design iterations to screen possible solutions, with only the most promising designs moving to the prototype stage. In principle, shortening a simulation from a previous runtime to half that time could allow engineers to test more variants within the same development schedule. A 30% reduction in structural-analysis time could provide a similar benefit for mechanical components.

That workflow does not eliminate physical testing. Simulation results depend on the accuracy of the model, the quality of its input data and validation against real-world behaviour. A faster calculation is useful only if it remains sufficiently representative of the component or airflow being studied.

Why simulation matters under the 2027 rules

The listed 2027 changes—including 850cc engines, reduced aerodynamics, a ban on ride-height devices, 100% sustainable fuel and a new tyre supplier—expand the engine, thermal, intake, mechanical and aerodynamic development work described by Lenovo.

The source also says that on-track testing is limited by MotoGP’s concessions system. That increases the value of computer-based development because engineers cannot rely on unlimited track time to compare physical designs.

HPC therefore acts as a way to move part of the design process away from the circuit. Engineers can use numerical models to eliminate less promising options before manufacturing components, potentially reducing the number of physical prototypes, development time and manufacturing costs. Lenovo provides no independent cost figures or production data showing the size of any such savings for Ducati.

The important distinction is between expanding the search space for designs and proving that one of those designs will perform better on track. The supplied evidence supports the former as Lenovo’s stated engineering objective, but does not establish any resulting improvement in lap time, reliability, race results or championship performance.

What the figures do—and do not—show

The reported specifications and reductions describe the computing infrastructure, not the motorcycle itself.

TFLOPS measures floating-point throughput: one TFLOP represents one trillion floating-point operations per second. The stated figure is a theoretical peak for combined double-precision performance. It does not directly measure the time required for a particular CFD or structural-analysis workload.

Similarly, the reported 50% and 30% reductions are attributed to Lenovo, but the source does not state:

  • the previous and new runtimes;
  • the hardware and software configurations;
  • the size or complexity of the models;
  • the benchmark procedure;
  • whether the figures apply across all workloads or selected simulations; or
  • how the simulations were validated against physical measurements.

The expansion also cannot, on the available evidence, be linked to any specific performance result from the 2027 motorcycle. The final bike has not been assessed in the supplied material, and no independent evidence is provided about its on-track speed, reliability or regulatory compliance.

What to watch

The most useful follow-up evidence would include independent benchmarks or technical details showing how the simulation reductions were measured. Information about the processors, accelerators, interconnects, simulation software, model sizes and validation process would make the performance claims easier to evaluate.

Future testing may help assess whether designs developed with this process perform well under the new regulations. On-track results alone, however, would not isolate the contribution of the HPC upgrade from the many other factors involved in developing and racing a motorcycle.

For now, the verified development is an infrastructure upgrade and a manufacturer-reported reduction in simulation time. It illustrates how HPC can support more virtual design iterations, but it does not by itself establish a faster or more reliable racing motorcycle.

Sources