Summary
Google announced TPU 8tx for confidential inference and TPU 8i Max for large-context workloads, expanding its eighth-generation TPU portfolio. The company describes them as new system configurations rather than two entirely new chip designs.
Google announced two additions to its eighth-generation Tensor Processing Unit (TPU) portfolio on Nov. 9, 2026: TPU 8tx, designed for confidential inference, and TPU 8i Max, aimed at workloads that need large context windows. The company says the additions bring its total to four TPU systems introduced in a single year, alongside TPU 8t and TPU 8i.
The announcement describes these as new systems, not two wholly new chip designs. Google says a system combines compute with elements such as networking, storage and packaging around a chip, allowing it to adjust configurations more quickly than the multi-year process of designing and manufacturing new silicon.
One system for confidential inference, another for memory-heavy work
TPU 8tx is intended for organisations running models and AI agents alongside sensitive data. Google says it uses the same silicon as TPU 8t, paired with 5th Generation AMD EPYC CPU hosts, and incorporates hardware-level confidential computing. The aim is to protect and isolate data and model weights while they are being processed, rather than only when stored or sent over a network.
The system also uses Google's Boardfly network, which the company says was developed for real-time reasoning. Google reports that TPU 8tx delivers up to 2× lower latency than TPU 8t with a near-zero performance penalty. It says the combination of training-grade compute and an inference network can support fine-tuning on private data, distillation and reinforcement learning on one system.
TPU 8i Max targets a different constraint: moving enough information to processors as AI workloads use very long contexts. High-bandwidth memory (HBM) supplies data to processors at high speeds; when that flow cannot keep up with computation, memory bandwidth can limit performance. Google says TPU 8i Max puts two TPU 8i chips on one package, providing twice the compute, twice the SRAM and twice the HBM bandwidth of TPU 8i. The company also says it fits twice the silicon within the existing rack footprint, increasing compute density per rack.
How the systems fit into Google's TPU lineup
Google positions TPU 8t for large-scale model training and TPU 8i for low-latency reasoning. The new 8tx configuration adds a focus on confidential computing, while 8i Max is designed for very large contexts and greater compute density. Together, the four systems address different stages and requirements of AI workloads rather than offering a single general-purpose configuration.
The announcement also points to Google's broader effort to make TPUs easier to use, including support for PyTorch and open-source serving software. That matters because accelerator hardware is useful to developers only when their software can run on it without extensive adaptation. Google says its recent software work is intended to reduce that barrier, alongside the specialised hardware configurations.
The performance and density figures in the announcement are Google's reported claims. It does not state measurement conditions for the TPU 8tx latency comparison or the 8i Max density figures.